SETS-THIRAL-PRINCE-Power-Protected-BRAM-FPGA

About Dataset

The traces were obtained by measuring the real-time Power consumption of an PRINCE encryption process. These measurements are highly suitable for Side-Channel Analysis (SCA), enabling cryptographic key recovery through both statistical techniques and deep learning–based approaches. Power traces were collected using KeySight DSOS204A Oscilloscope, with the bandwidth of 2GHz and Sampling rate of 20GS/s connected to an Kintex-7 FPGA. Trigger-based synchronization is used during acquisition process to align the captured traces with encryption operations. After collection, the traces were formatted and annotated with appropriate labels to support side-channel analysis experiments and AI model development. The dataset is provided in HDF5 (.h5) format and is divided into Profiling_traces and Attack_traces groups. The Profiling_traces group consists of 100,000 power traces, each containing 70,002 sample points along with a metadata structured array containing the corresponding plaintext, key, and ciphertext values and a label array. The Attack_traces group contains 20,000 power traces together with the corresponding metadata structured array. The labels correspond to the most significant nibble (MSB nibble) of the first-round S-box output for byte 0 of the plaintext. Label generation uses plaintext byte 0 (PT [0]) and the 128-bit PRINCE master key. The master key is divided into two 64-bit subkeys, K0 and K1. A derived key byte is obtained from the XOR of K0 and K1, and the byte at position 0 (K0 XOR K1) [0], is used in the first-round computation. The intermediate value is computed by XORing PT [0] with (K0 XOR K1) [0], and the result is passed through the PRINCE S-box. The resulting 8-bit S-box output is divided into its most significant nibble (bits 7-4) and least significant nibble (bits 3-0). The most significant nibble is used as the class label, resulting in 16 classes (0-15). BRAM Write Collision (BWC) is a hiding-based countermeasure that exploits the behavior of dual-port Block RAM (BRAM) resources available in FPGA devices. The simultaneous writes of different data values to the same address in a dual-port BRAM can create internal contention, resulting in increased switching activity that is independent of the cryptographic operation being performed. The additional power consumption generated by these write collisions acts as noise and reduces the signal-to-noise ratio of side-channel leakage. In the SETS-THIRAL repository, the BWC countermeasure was implemented using 16 dual-port BRAM instances, each configured with a 36-bit data width. Both ports of a BRAM were driven with different data values while accessing the same address location, thereby inducing write collisions. The write-enable signals, addresses, and input data were generated using lightweight feedback-based registers to continuously vary the collision patterns during cryptographic execution. The BRAM collision logic operated concurrently with the cryptographic engine, producing additional data-independent switching activity throughout the cryptographic process. Datasets collected from these implementations enable the evaluation of side-channel analysis techniques against FPGA implementations protected using BRAM-based noise generation.