SETS-THIRAL-AES128-Power-Protected-SRL-MC

About Dataset

The traces were obtained by measuring the real-time power consumption of an AES-128 encryption process during its first round. These measurements are highly suitable for Side-Channel Analysis (SCA), enabling cryptographic key recovery through both statistical techniques and deep learning–based approaches. Power consumption data were collected using a ChipWhisperer CW1200 platform connected to an ATxmega microcontroller. Trigger-based synchronization is used during acquisition process to align the captured traces with encryption operations. After collection, the traces were formatted and annotated with appropriate labels to support side-channel analysis experiments and AI model development. The dataset is provided in HDF5 (.h5) format and is divided into Profiling_traces and Attack_traces groups. The Profiling_traces group consists of 150,000 power traces, each containing 95,000 sample points along with a metadata structured array containing the corresponding plaintext, key, and ciphertext values and a label array. The Attack_traces group contains 20,000 power traces together with the corresponding metadata structured array. Labels are generated from the first-round S-box output of the AES-128 encryption algorithm. For each trace, plaintext byte 2 (PT[2]) is XORed with byte 2 of the secret key (K[2]). The resulting value is passed through the AES S-box, and the resulting 8-bit S-box output is used to derive the label. The labels correspond to the complete S-box output value, resulting in 256 possible classes ranging from 0 to 255. The Shift Register LUT (SRL) countermeasure is a hiding-based software technique designed for 8-bit microcontroller implementations. It is implemented using an array initialized with random values, on which circular shift operations are performed to introduce additional computational activity that is independent of the sensitive data being processed. In the SETS-THIRAL dataset, the SRL is inserted at randomly selected positions within the first round of the cryptographic computation. For each encryption, one of several predefined execution sequences is chosen randomly, causing the SRL to execute at different stages of the first round. This random insertion results in trace misalignment and temporal desynchronization across encryptions, thereby enhancing the implementation's resistance to side-channel attacks.