SETS-THIRAL-AES128-Power-Protected-BRAM-FPGA

About Dataset

The traces were obtained by measuring the real-time power consumption of an BRAM protected AES-128 encryption process. These measurements are highly suitable for Side-Channel Analysis (SCA), enabling cryptographic key recovery through both statistical techniques and deep learning–based approaches. Power consumption data were collected using Agilent Technologies MSO7104B Oscilloscope, with the bandwidth of 1GHz and Sampling rate of 4GS/s connected to an Kintex-7 FPGA. Trigger-based synchronization is used during acquisition process to align the captured traces with encryption operations. After collection, the traces were formatted and annotated with appropriate labels to support side-channel analysis experiments and AI model development. The dataset is provided in HDF5 (.h5) format and is divided into Profiling_traces and Attack_traces groups. The Profiling_traces group consists of 100,000 power traces, each containing 10,000 sample points along with a metadata structured array containing the corresponding plaintext, key, and ciphertext values and a label array. The Attack_traces group contains 20,000 power traces together with the corresponding metadata structured array. Labels are generated from the first-round S-box output of the AES-128 encryption algorithm. For each trace, plaintext byte 2 (PT[2]) is XORed with byte 2 of the secret key (K[2]). The resulting value is passed through the AES S-box, and the resulting 8-bit S-box output is used to derive the label. The labels correspond to the complete S-box output value, resulting in 256 possible classes ranging from 0 to 255. BRAM Write Collision (BWC) is a hiding-based countermeasure that exploits the behavior of dual-port Block RAM (BRAM) resources available in FPGA devices. The simultaneous writes of different data values to the same address in a dual-port BRAM can create internal contention, resulting in increased switching activity that is independent of the cryptographic operation being performed. The additional power consumption generated by these write collisions, acts as noise and reduces the signal-to-noise ratio of side-channel leakage. In the SETS-THIRAL repository, the BWC countermeasure was implemented using 16 dual-port BRAM instances, each configured with a 36-bit data width. Both ports of a BRAM were driven with different data values while accessing the same address location, thereby inducing write collisions. The write-enable signals, addresses, and input data were generated using lightweight feedback-based registers to continuously vary the collision patterns during cryptographic execution. The BRAM collision logic operated concurrently with the cryptographic engine, producing additional data-independent switching activity throughout the cryptographic process. Datasets collected from these implementations enable the evaluation of side-channel analysis techniques against FPGA implementations protected using BRAM-based noise generation.